1. Field of the Invention
The present invention relates to semiconductor devices and their manufacture, including but not limited to a method of making field effect transistors (FETs) such as FETs having embedded stressor elements and FETs of the finFET type.
2. Description of the Related Art
Various types of semiconductor devices incorporate epitaxial semiconductor layers to provide essential function therein. An epitaxial layer is a layer of monocrystalline semiconductor material which grows outward from an exposed surface of an existing monocrystalline semiconductor region or layer. An epitaxial semiconductor layer can be grown on an exposed semiconductor surface which coincides with a major surface of a wafer. The epitaxial layer may have the same composition as the semiconductor region on which it is grown, e.g., the semiconductor material, impurities, e.g., dopants and their concentrations, or the compositions of the epitaxial layer and the underlying semiconductor region can be different. Sometimes, the epitaxial layer has characteristics that allow the epitaxial layer to impart a stress to the semiconductor region on which it is grown. For example, an epitaxial semiconductor layer can impart a stress to an adjacent semiconductor region when the epitaxial semiconductor region comprises a semiconductor alloy material different from the adjacent semiconductor region such that epitaxial layer has a different crystal lattice constant than the lattice constant of the adjacent semiconductor region.
Sometimes, a second epitaxial layer is grown on top of a first epitaxial semiconductor layer, and sometimes one or more additional layers are grown thereon in layer upon layer fashion in making a semiconductor device. FIG. 1 illustrates one possible result when epitaxial layers of semiconductor material are grown within an opening 12 in a semiconductor region 10, the opening having a lower surface 13 defining a depth of the opening from a major surface 14 of the semiconductor region. The opening may also have interior surfaces, e.g., walls 16 which rise in a direction from the lower surface 13 towards the major surface 14. These walls 16 can extend in a vertical direction away from the major surface 14 or the lower surface 13 or both, or may extend in one or more other directions which rise from the lower surface towards the major surface.
As epitaxial growth processes tend to promote growth of a semiconductor layer on exposed <100> crystallographic planes of a semiconductor wafer which is parallel to the major surface of the wafer, a structure such as seen in FIG. 1 may result when first and second epitaxial layers 18, 20 are grown successively within the opening 12.
In such example, growth of the layer 18 on the lower surface 13 at which the <100> crystallographic plane of the semiconductor region is exposed and growth on the wall surfaces 16 at which the <110> crystallographic plane is exposed may occur with about the same rate. As a result, the thickness of the layer 18 overlying the lower surface 13 is about the same as the thickness of the layer 18 overlying each of the wall surfaces 16. The thickness of the resulting layer 18 may even be greater on the lower surface 13 than on the wall surfaces 16. The second layer 20 is grown onto the first epitaxial layer 18 thereafter. The second layer may serve a different purpose than the first layer, and the dopant concentrations of the layers 18, 20 may be different. Further processing may be performed to provide an electrically conductive path within the semiconductor material from the underlying semiconductor region 10 to the second epitaxial layer 20. For example, an anneal can be performed, which among other results, can cause dopant which may exist in higher concentration in the underlying semiconductor region 10 to diffuse upward from the semiconductor region 10 across lower surface 13 into the first layer 18. However, when the first layer 18 has a relatively low dopant concentration and the thickness of the first layer 18 adjacent the lower surface is relatively high, this can make it difficult to form the electrically conductive path between the semiconductor region 10 and the second layer 20.
FIG. 2 illustrates another structure 30 where an epitaxial semiconductor layer needs to be grown on wall surfaces of an existing semiconductor region. In such example, the semiconductor region can include a plurality of parallel fins 32 which rise above a surface 33 of an underlying oxide layer, such as a buried oxide (BOX) layer 34. The fins 32 in such example can be fins which extend into a source-drain region of a finFET having the same fins with gates overlying the fins in a gate region 28, for example. In the source-drain region, the finFET may include epitaxial layers 38 which fill in the space between adjacent fins 32 to form a continuous source-drain region of semiconductor material.
In this case, the epitaxial layer does not grow on the BOX layer. However, because growth must occur primarily on wall surfaces 36 of the fins which are exposed <110> crystallographic planar surfaces, the epitaxial layer 38 grows faster at locations of the wall surfaces 36 which are not very close to the BOX layer. As a result, the epitaxial layers 38 on fins 32 which are directly adjacent to one another grow together to form a seam 40 at locations well above the BOX layer surface 33, so that voids 42 remain in the epitaxial layers 38 adjacent to the BOX layer surface 33. It is undesirable for voids to remain in the structure because impurities may become trapped or concentrated therein, and voids may lead to premature failure or performance degradation. In addition, because the semiconductor material of the epitaxial layer 38 is missing at the bottoms of the fins adjacent the BOX layer surface 33, there is no semiconductor material present there as a source of dopant available to diffuse into the fins 32 during a subsequent drive-in anneal which can be performed after growing the epitaxial layer 38. This too can be undesirable.
Thus, it would be desirable to provide improvements to a process of forming epitaxial layers on wall surfaces, e.g., exposed <110> crystallographic plane surfaces, of semiconductor regions.